STS and University of Alaska Fairbanks enters in an exclusive agreement to supply High Reliability 3D stacked products to Aerospace & DOD customers, utilizing Tessera's Inc., CSP and stacking technology.
STS is an engineering driven Qualification Laboratory for your IC qualification and reliability evaluation needs. We bridge the gap and provide an extension to your in house engineering talent and provide a complete one stop service for electrical and environmental screening of ICs.
STS specializes in services aimed at assessing the long-term reliability of Integrated Circuits, their suitability of use, their interaction in sub-systems, field use, and storage conditions. Our services characterize, evaluate, compare, and assess wafer processing, foundry sources, and assembly processing. Our capabilities include the evaluation of packaging technologies such as QFP, BGA, Chip Scale, Flip Chip, and High Density Interconnect packages.
STS employs advanced state-of-the-art test equipment to provide reliability solutions for ICs, tools for materials analysis including Acoustic Imaging, (CSAM), real-time X-ray imaging, Shadow Moiré, and others. Device and Failure analysis using advanced non-contact techniques (IDS), EMMI, FIB, SEM and EDS, are available for an "integrated turnkey solution"
STS provides full services for the Design and Assembly of all necessary hardware, including Boards for Burn-in, HAST, ESD, Latch-up, 85/85, and custom designs. Our services include maintenance, calibration and repair of all hardware.
STS provides a standard comprehensive reliability test report, with unbiased dependable data for critical predictions of the life cycle and reliability of your product. The "device analysis" reports are designed to pin point failures and propose solutions / strategies to improve product reliability.
The process of electrical and environmental screening is singularly encumbered with guaranteeing the conformance of the integrated circuit to the reliability and functional characteristics demanded by the application of the IC. Electrical testing, using ATE, while effective for removing the in process rejects, still leaves the Component engineer with a challenge. The practice of using the conventionally prescribed set of tests and test conditions is now unacceptable, as they often produce false failures or may not accelerate valid failures because the stress conditions may not correlate with the actual "use" environments. STS understands the challenges, and works with customers to device reliability tests with the knowledge of the customer's application conditions and can assist in devising acceleration models and activation energies associated to application conditions. Let the professionals at STS offer our expertise to assist your company in defining and selecting stress tests, thermal and environmental aging tests, and product life cycles.
